1. Field of the Invention
The present invention relates generally to systems and methods for testing circuit design descriptions, and more particularly to systems and methods for automated design description verification within an electronic design automation (EDA) environment.
2. Discussion of Background Art
Electronic Design Automation (EDA) is a process for using computer programs to design, simulate, and test electronic circuits before they are fabricated. By simulating designs with simulation software, on emulation systems, and/or by using simulation acceleration systems, design flaws are detected and corrected before fabrication of the silicon device. A testing before fabrication process saves manufacturers millions of dollars in non-recoverable engineering (NRE) costs. However, as designs increase in complexity, so too does the difficulty of testing. In fact, the difficulty of testing with traditional EDA verification tools increases geometrically with the number of gates. System designers are also asked to design and test these increasingly complex circuits within ever smaller time frames. As a result, manufacturers must choose between either taking more time to test the design, and thereby delaying product shipment, or only testing portions of the circuit, and thereby risking that many undiscovered bugs get passed on to the users.
One approach to this problem is to speed up the design simulation programs. Native Code Simulators, Simulation Acceleration, and Chip Emulation System all decrease the time it takes to simulate a design, and may sometimes decrease the time it takes to identify the next bug in a design. However, during early stages of the design process, design bugs are prevalent, and speeding up the simulation does little to help identify these bugs.
Another approach is to test the circuit design randomly. Random testing involves generating a plurality of unique test vectors that are randomly related to each other and then testing (or xe2x80x9cexercisingxe2x80x9d) the design with these vectors. In this approach, as time allotted for random testing increases, more of the circuit design is tested. Random testing is a time consuming and risky proposition, since discovering bugs then becomes a hit or miss proposition, and there is rarely sufficient time to test the circuit design fully. Moreover, it is quite possible, even likely that running a random simulation for ten or one hundred times longer will not significantly increase the verification density.
Other types of EDA testing tools, such as an Automatic Test Pattern Generation (ATPG) tools, produce tests which only identify manufacturing defects in an already fabricated circuit. Testing is performed by successively applying known input values to the pins of the circuit, and then comparing actual output values with a set of expected output values. However, ATPG tools assume that the circuit already has a fundamentally correct design and that any anomalies that are discovered are only due to physical defects introduced in the manufacturing process, such as broken wires.
EDA testing tools, such as Verilint, developed by InterHDL of Los Altos, Calif.; Vericov, developed by Simulation Technology of Saint Paul, Minn.; Vera, developed by System Science of Palo Alto, Calif.; and Specman, developed by Verisity of Yehud, Israel; also exist but they are difficult to use, sell, and integrate into a test bench for verifying the correctness of circuit designs.
What is needed is an apparatus and method for design verification that overcomes the problems of the prior art.
The present invention is a system and a method for automated design verification. Within the system of the present invention, a test bench is created to stimulate a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies which portions of the design remain to be tested. A test generator produces test vectors and sends them to the test bench which exercises the portions of the simulated design which the coverage analysis tool has indicated remain to be tested. With the method of the present invention, a design description is interpreted by a test generator as a state diagram composed of a set of basic blocks interconnected by transition arcs. The test generator produces a plurality of test vectors for exercising the basic blocks and transition arcs. A computer program processes the design description and creates a simulated design. Basic blocks and transition arcs within the simulated design are exercised by the plurality of test vectors. Those basic blocks and transition arcs which have (and have not) been exercised are identified by a coverage analysis program which monitors the simulated design""s internal operation. The test generator receives these reports and in response produces a new set of test vectors to exercise the basic blocks and transition arcs which were not yet tested. A first set of output data from the simulated design may then be compared against a second set of output data received from a reference. The first set of output data may also be compared with a set of optional constraints. These comparisons result in an anomaly report if the first set of output data is not equivalent to either the second set of output data or the set of optional constraints. The test generator then correlates the basic blocks and transition arcs exercised by the test vectors with the results from the reporting step to localize and identify any of the basic blocks and transition arcs within the simulated design which were operating incorrectly or indeterminately.
The apparatus and method of the present invention are particularly advantageous over the prior art because a critical part of design verificationxe2x80x94previously performed, manually and on a sporadic basis due to engineering resource requirements and time-to-market considerationsxe2x80x94is now automated. The present invention permits testing of basic blocks, transition arcs, and paths of interest within the simulated design using a quick, easy, comprehensive, and integrated process. As a result, designers can proceed toward fabrication with confidence that the simulated design has been verified. A time savings of months is achieved, since any design flaws are discovered before the simulated design is fabricated.